1. Field of the Invention
The present invention relates to static random access memories (hereinafter referred to as static RAMs) and, more specifically, to a static RAM in which reading angle can be arbitrary set to 0.degree., 90.degree., 180.degree. and 270.degree..
2. Description of the Background Art
In image processing by a printer, a word processor, a copying machine or by a high vision television, images to be displayed are often subjected to X-Y conversion (reading angle rotation) with respect to original image data. The reading angle rotation is indispensable when characters written laterally are changed to be written vertically, or when characters are to be printed on a rear surface of a sheet-of paper by a printer, for example. FIGS. 13 (a), (b), (c) and (d) are examples of reading angle rotation by the angle of 0.degree., 90.degree., 180.degree. and 270.degree., respectively, of the character "A".
FIG. 14 shows a concept of an example of a conventional method for X-Y converting an original character by a prescribed angle. For different fonts of the character "A" provided by rotating the character by 0.degree., 90.degree., 180.degree. and 270.degree. are stored in four font memories 200, 201, 202 and 203 formed of, for example, read only memories (ROMs), as shown in FIG. 14. A necessary font is selected from four font memories 200, 201, 202 and 203 by a switch 204, and the necessary font is generated at an output terminal 205.
In this method, speed of conversion is fast. However, it requires a memory of large storage capacity for storing a large number of fonts. In addition, this method cannot be applied to ever changing data such as outputs from a video camera.
In another conventional method, only one type of font is prepared for each character, and the font is converted by a desired angle to be outputted by means of software using a controller such as a MPU (Micro Processing Unit), a MCU (Memory Control Unit) or the like. However, in this method, the speed of conversion is very slow.
FIG. 15 is a block diagram showing a structure of a main portion of a conventional static RAM by which displayed images can be moved, inclined or rotated at high speed. This static RAM is disclosed in Japanese Patent Laying-Open No. 63-53783.
An X axis address decoder DDCRX, an X axis column switch CSWX, an X axis shift register SRX, a Y axis address decoder DCRY, a Y axis column switch CSWY and a Y axis shift register SRY are connected to a memory array M-ARY. An input/output circuit I/O is provided for inputting and outputting data.
FIG. 16 shows a detailed structure of the memory array M-ARY. Referring to FIG. 16, memory array M-ARY includes a plurality of X axis word lines WX0 to WXn and a plurality of sets of X axis complementary data lines DX0, DX0 to DXn,/DXn arranged in the vertical direction of the figure, and a plurality of Y axis word lines WY0-WYn and a plurality of sets of Y axis complementary data lines DY0,/DY0 to DYn,/DYn arranged in the horizontal direction of the figure. Memory cells MC00-MCnn are arranged at crossings of the word lines and complementary data lines.
X axis word lines WX0-WXn are coupled to X axis address decoder DCRX, and X axis complementary data lines DX0,/DX0 to DXn,/DXn are connected to corresponding bits of X axis shift register FRX through X axis column switch CSWX. X axis column switch CSWX includes a plurality of sets of switch MOSFETs Q7, QS, . . . , Q9 and Q10. x axis complementary data lines DX0,/DX0-DXn, /DXn are coupled to X axis complementary common data lines CDX and/CDX through switch MOSFETs Q7, Q8-Q9 and Q10. Data line selecting signals DX0-DXn from X axis address decoder DCRX are applied to the gates of each sets of switch MOSFETs Q7, Q8-Q9 and Q10.
X axis complementary common data lines CDX and/CDX are connected to input/output circuit I/O. The leading bit and the last bit of X axis shift register SRX are connected to the input/output circuit I/O through serial data signal lines SDX and/SDX.
Any of the plurality of X axis word lines WX0-WXn is selected by X axis address decoder DCRX, or any of the plurality of sets of X axis complementary data lines DX0, DX0 to DXn, /DXn is selected.
Similarly, Y axis word lines WY0-WYn are coupled to Y axis address decoder DCRY, and Y axis complementary data lines DY0,/DY0 to DYn,/DYn are coupled to Y axis shift register SRY through Y axis column switch CSWY.
Any of the plurality of Y axis word lines WY0-WYn is selected by Y axis addressdecoder DCRY, or any of the plurality of sets of Y axis complementary data lines DY0, DY0 to DYn,/DYn is selected.
As described above, each memory cell of memory array M-ARY is coupled to an X axis word line, X axis complementary data lines, a Y axis word line and Y axis complementary data lines. Therefore, it can be accessed from the X axis through the X axis word line and Y axis complementary data lines, and from Y axis through the Y axis word line and X axis complementary data lines.
It is possible to read data stored in a memory cell coupled to the selected word line to a shift register, to shift the data for a prescribed number of times, and to write the shifted data to a memory cell of the memory array. By repeating such shifting operation, displayed image can be moved in horizontal or vertical direction, inclined or rotated at high speed.
In the above described static RAM, each memory cell includes resistances R1 and R2 and MOSFETs Q1 and Q2 constituting a latch circuit. For example, in a memory cell MC00, nodes N1 and N2 are connected to the Y axis complementary data lines DY0 and/DY0 through MOSFETs Q3 and Q4 serving as access gates, and connected to X axis complementary data lines DX0 and/DX0 through MOSFETs Q5 and Q6 serving as access gates.
In this manner, in the memory cell of FIG. 16, complementary data are written to two nodes N1 and N2 through X axis complementary data lines or Y axis complementary data lines, and complementary data are read from two nodes N1 and N2 through X axis complementary data lines or Y axis complementary data lines. Therefore, four access gates and sixth signal lines are necessary. Consequently, the number of elements and the circuit area are increased, and interconnections inevitably become complicated.
In the above described static RAM, write drivers DRa and DRb and a sense amplifier SXa are connected to X axis complementary data lines DX0,/DX0, and at least a sense amplifier SAY is connected to Y axis complementary data lines DY0, /DY0.
Similarly, write drivers and sense amplifiers are connected to other X axis complementary data lines, and similarly sense amplifiers are connected to other Y axis complementary data lines.
Write driver DRa includes P channel MOSFETs Q51, Q52 and N channel MOSFETs Q53, Q54, while write driver DRb includes P channel MOSFETs Q55, Q56 and N channel MOSFETs Q57, Q58. Input data Din is applied to the gates of the transistors Q52 and Q53 of the write driver DRa, and input data Din is applied to the gates of transistors Q56 and Q57 of write driver DRb through an inverter G11. Write drivers DRa and DRb are controlled by a write enable signal WE and its inverted signal/WE. Sense amplifier SAX includes P channel MOSFETs Q59, Q60 and N channel MOSFETs Q61, Q62, while sense amplifier SAY includes P channel MOSFETs Q63, Q64 and N channel MOSFETs Q65, Q66. Sense amplifiers SAX and SAY provides output data DO, respectively.
In this manner, in the above described static RAM, 12 MOSFETs and one inverter are necessary for the write drivers and sense amplifier connected to a set of X axis complementary data lines, and 4 MOSFETs are necessary for the sense amplifier connected to one set of Y axis complementary data lines. Consequently, the number of elements and the circuit area increase in the peripheral circuit, and the interconnection becomes complicated.